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XRT91L306 Datasheet(PDF) 7 Page - Exar Corporation |
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XRT91L306 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 39 page xr XRT91L30 REV. 1.0.1 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 5 CDRREFSEL LVTTL, LVCMOS I 60 Clock and Data Recover Unit Reference Frequency Select Selects the Clock and Data Recovery Unit reference frequency based on the table below. "Low" = CDR uses CMU’s reference clock "High" = CDR reference clock from CDRAUXREFCLK NOTE: CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 500ppm. LOOPTIME LVTTL, LVCMOS I 2 Loop Timing Mode When the loop timing mode is activated the external reference clock to the input of the Retimer is replaced with the high-speed recovered receive clock from the CDR. "Low" = Disabled "High" = Loop timing Activated CDRDIS LVTTL, LVCMOS I 12 Clock and Data Recovery Unit Disable Active "High." Disables internal Clock and Data Recovery unit. Received serial data bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of externally recovered differential clock XRXCLKIP/N coming from the opti- cal module. "Low" = Internal CDR unit is Enabled "High" = Internal CDR unit is Disabled and Bypassed PIO_CTRL LVTTL, LVCMOS I 48 Transmit Parallel Clock Directional Control Transmit Parallel Clock Output Operation If this pin is asserted "High", TXPCLK_IO is a parallel bus clock output. Data on the TXDI[7:0] must be synchronously applied prior to the sampling by the PISO at the rising edge of TXPCLK_IO clock output driven by the XRT91L30. Alternate Transmit Parallel Clock Input Operation Asserting this control pin "Low" or if left unconnected, it config- ures TXPCLK_IO to serve as a parallel bus clock input rather than a parallel bus clock output and permits the XRT91L30 to accept the external clock input. Data on the TXDI[7:0] is then sampled at the rising edge of the TXPCLK_IO clock input driven by the framer/mapper device. "Low" = TXPCLK_IO is a Parallel Clock Input. "High" = TXPCLK_IO is a Parallel Clock Output. NOTE: Parallel Clock Input operation has the advantage of permitting the framer/mapper device timing to be synchronized with the transceiver transmitter timing. This pin is provided with an internal pull-down. NAME LEVEL TYPE PIN DESCRIPTION CDRREFSEL STS12/ STS3 CDRAUXREFCLK FREQUENCY DATA RATE 0 CDR uses CMU’s reference clock (see CMUFREQSEL pin) 10 77.76 MHz STS-3/STM-1 155.52 Mbps 11 77.76 MHz STS-12/STM-4 622.08 Mbps |
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Similar Description - XRT91L306 |
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