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XRT91L80 Datasheet(PDF) 8 Page - Exar Corporation |
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XRT91L80 Datasheet(HTML) 8 Page - Exar Corporation |
8 / 45 page XRT91L80 PRELIMINARY xr xr xr xr 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.1.0 6 LOOPTM_JA LVTTL, LVCMOS I C6 Loop Timing Mode With Jitter Attenuation The LOOPTM_JA pin must be set "High" in order to select the recovered receive clock as the reference source for the de-jitter PLL. "Low" = Disabled "High" = Loop timing with de-jitter PLL Activated This pin is provided with an internal pull-down. LOOPTM_NOJA LVTTL, LVCMOS I P2 Loop Timing Mode With No Jitter Attenuation When the loop timing mode is activated, the external local refer- ence clock input to the CMU is replaced with the 1/16th or 1/ 32nd of the high-speed recovered receive clock coming from the CDR. "Low" = Disabled "High" = Loop timing Activated This pin is provided with an internal pull-down. TRANSMITTER SECTION NAME LEVEL TYPE PIN DESCRIPTION TXDI0P TXDI0N TXDI1P TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N LVDS I H13 J13 K14 L14 K13 L13 M14 N14 Transmit Parallel Data Input The 622.08 Mbps 4-bit parallel transmit data input should be applied to the transmit parallel bus simultaneously to be sam- pled at the rising edge of the TXPCLKIP/N input. The 4-bit par- allel interface is multiplexed into the transmit serial output interface MSB first (TXDI3P/N). NOTE: The XRT91L80 can accept 666.51 Mbps 4-bit parallel transmit data input for Forward Error Correction (FEC) Applications. TXPCLKIP TXPCLKIN LVDS I H14 J14 Transmit Parallel Clock Input 622.08 MHz clock input used to sample the 4-bit parallel trans- mit data input TXDI[3:0]P/N. NOTE: The XRT91L80 can accept a 666.51 MHz transmit clock input for Forward Error Correction (FEC) Applications. TXOP TXON CMLDIFF O K1 L1 Transmit Serial Data Output The transmit serial data output stream is generated by multi- plexing the 4-bit parallel transmit data input into a 2.488 Gbps serial data output stream. In Forward Error Correction, the transmit serial data output stream is 2.666 Gbps. REFCLKP REFCLKN LVPECL I P6 N6 Reference Clock Input This differential clock input reference is used for the transmit clock multiplier unit (CMU) to provide the necessary high-speed clock reference for this device. Pin ALTFREQSEL determines the value used as the reference. See Pin ALTFREQSEL for more details. VCXO_INP VCXO_INN LVPECL I P4 N4 Voltage Controled Oscillator Input This differential clock input is used for the transmit PLL jitter attenuation. Pin ALTFREQSEL determines the value used as the reference. See Pin ALTFREQSEL for more details. HARDWARE COMMON CONTROL NAME LEVEL TYPE PIN DESCRIPTION |
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