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XRT91L80IB Datasheet(PDF) 1 Page - Exar Corporation |
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XRT91L80IB Datasheet(HTML) 1 Page - Exar Corporation |
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1 / 45 page  Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr xr xr xr PRELIMINARY XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JULY 2005 REV. P1.1.0 GENERAL DESCRIPTION The XRT91L80 is a fully integrated SONET/SDH transceiver for SONET OC-48/STM-16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high- speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on- chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial- to-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the FIFO_AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU, LOCKDET_CDR, and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS • SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches and Routers • DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment FIGURE 1. BLOCK DIAGRAM OF XRT91L80 PISO (Parallel Input Serial Output) PFD & Charge Pump TXDI0P/N Serial Microprocessor Hardware Control TXDI1P/N TXDI2P/N TXDI3P/N TXPCLKIP/N DLOOP RLOOPP RXDO0P/N RXDO1P/N RXDO2P/N RXDO3P/N WP RP RLOOPS CDR Re-Timer CMU TXOP/N RXIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16DIS FIFO_RST FIFO_AUTORST LOSDMUTE DISRD STS-48 TRANSCEIVER JTAG TDO TDI TCK TMS TRST Div by 4 Div by 16 RXPCLKOP/N RXCLKO16P/N Div by 4 Div by 16 SIPO (Serial Input Parallel Output) |
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