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XRT6164A Datasheet(PDF) 6 Page - Exar Corporation |
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XRT6164A Datasheet(HTML) 6 Page - Exar Corporation |
6 / 10 page XRT6164A 6 Rev. 3.0.0 SYSTEM DESCRIPTION The XRT6164A is a general purpose line interface chip that con tains the receive and transmit circuitry necessary to convert TTL logic levels to a CMOS signal both to and from a twisted pair cable. Receiver The XRT6164A receiver section converts a balanced CMOS signal that has been attenuated and distorted by up to 10dB of twisted pair cable to active-low TTL- compatible logic levels. The cable is transformer coupled to the receiver differ- ential inputs (RX+IP, RX-IP) which are biased through the input transformer secondary winding by a voltage generated on-chip (I/P BIAS). The CMOS receive signal is applied to a peak detector, and to a pair of data comparators. The peak detector output voltage charges an external capacitor connected to PEAK CAP. This voltage generates a data comparator bias level that is approximately 50% of the peak input pulse amplitude. Thus, data slicing is automatically accomplished at the optimum level over the full cable loss range. TTL- compatible output stages buffer the receiver digital outputs (S+R, S-R) and provide active low signals corresponding to received positive and negative input pulses. Loss of input signal is detected by a comparator that monitors input signal level. An active-low TTL-compat- ible logic level (RX ALARM) indicates signal loss. Comparator hysteresis prevents chatter on this output. Ping-pong operation is made possible by the time compression multiplex control input (TCM CON). A logic 0 applied to this pin during transmission stores the peak detector output voltage by disconnecting the peak detector storage capacitor charge and discharge paths. Since the receive data comparator bias voltage is stored during transmit mode, it is immediately available when receive mode resumes. Transmitter The XRT6164A transmitter section contains two matched open collector output drivers that are capable of driving the line transformer directly with a current up to 40mA. The transmitter output drivers include diode clamps to ensure non-saturating operation. Transmit- ter digital inputs, which are active-low, are TTL-compat- ible. External resistors are used between the transmit- ter outputs and the output transformer primary to set the output pulse amplitude. APPLICATION INFORMATION Figure 2 shows a general line driver application circuit using the XRT6164A. This device converts CMOS transmit and receive signals in the 64Kbps to 1.544Mbps range to active-low TTL-compatible logic levels. CMOS signals that have been attenuated and distorted by twisted pair cable are transformer-coupled to the line side of the XRT6164A as shown on the left side of Figure 2. Suggested transformers for both the input and output applications are the Pulse types PE- 65535 or TTI-7147 for 64Kbps use and the PE-65835 for 1.544Mbps applications. The right side of Figure 2 shows the TTL-compatible digital inputs and outputs. Please refer to the pin description section of this data sheet for detailed information about each signal. |
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