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XRT7295AEIW Datasheet(PDF) 7 Page - Exar Corporation |
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XRT7295AEIW Datasheet(HTML) 7 Page - Exar Corporation |
7 / 15 page XRT7295AE 7 Rev. 2.0.0 internally generated jitter is a function of the PLL bandwidth, which in turn is a function of the input 1s density. For higher 1s densities, the amount of gener- ated jitter decreases. Generated jitter also depends on the quality of the power supply bypassing networks used. Figure 8 shows the suggested bypassing net- work, and Table 3 lists the typical generated jitter performance achievable with this network. Figure 4. Pulse Mask at the 34.368 Mbit/s Interface Parameter Value Pulse Shape (Nominally Rectangular) All marks of a valid signal must conform with the mask (see Figure 4), irrespective of the sign Pair(s) in Each Direction One coaxial pair Test Load Impedance 75 Ω Resistive Nominal Peak Voltage of a Mark (Pulse) 1.0V Peak Voltage of a Space (No Pulse) 0V +/-0.1V Nominal Pulse Width 14.55ns Ratio of the Amplitudes of Positive and Negative Pulses 0.95 to 1.05 at the Center of a Pulse Interval Ratio of the Widths of Positive and Negative Pulses 0.95 to 1.05 at the Nominal Half Amplitude Table 2. E3 Pulse Specification at the Transmitter Output Port |
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