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XRT8000 Datasheet(PDF) 10 Page - Exar Corporation |
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XRT8000 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 24 page XRT8000 10 Rev. 1.11 CR2 Register (Power On State = “00000”) D0 (PL2EN): Enable control for PLL2. If PL2EN = “1”, then PLL2 is enabled. Otherwise, if PL2EN = “0”, PLL2 is disabled. D1~D4 (M1~M4): Control bits for prescaler divider. These bits will set the divide ratio of the prescaler such that in MASTER/ FORWARD or REVERSE modes the output of this block is always at 8kHz. The settings for M4~M1 bits is based on the input frequency and the mode of operation (which is determined by the state of IOC4~IOC1 bits) is provided in Table 3. M4 M3 M2 M1 Mode Input Freq.[kHz] 0 0 0 0 Forward 1x(1544 or 2048) 0 0 0 1 Forward 2x(1544 or 2048) 0 0 1 0 Forward 3x(1544 or 2048) 0 0 1 1 Forward 4x(1544 or 2048) 0 1 0 0 Forward 5x(1544 or 2048) 0 1 0 1 Forward 6x(1544 or 2048) 0 1 1 0 Forward 7x(1544 or 2048) 0 1 1 1 Forward 8x(1544 or 2048) 1 0 0 0 Forward 9x(1544 or 2048) 1 0 0 1 Forward 10x(1544 or 2048) 1 0 1 0 Forward 11x(1544 or 2048) 1 0 1 1 Forward 12x(1544 or 2048) 1 1 0 0 Forward 13x(1544 or 2048) 1 1 0 1 Forward 14x(1544 or 2048) 1 1 1 0 Forward 15x(1544 or 2048) 1 1 1 1 Forward 16x(1544 or 2048) x x x x Reverse 56 x x x x Reverse 64 Note : This table applies to MASTER (FORWARD, REVERSE) mode only Table 3. CR2 Register |
Similar Part No. - XRT8000_06 |
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Similar Description - XRT8000_06 |
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