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XRT8000 Datasheet(PDF) 7 Page - Exar Corporation |
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XRT8000 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 24 page XRT8000 7 Rev. 1.11 SYSTEM DESCRIPTION On power up the clock outputs of XRT8000 will be tri-stated. This means that no clocks will be seen at the outputs and lock detect output will be low. After power up the XRT8000 needs to be initialized. Therefore a serial interface is provided to load the internal registers. These registers will define the modes of operation, the output frequencies and enabling the clock outputs. Master/Forward Mode of Operation When the XRT8000 device is operating in the “Master/Forward” Mode, it will receive either an “n x 2.048 MHz” or “n x 1.544 MHz” clock signal at the FIN input (pin3); where “n” can range from 1 to 16. From this input signal, the XRT8000 device will internally divide and synthesize the following signals. At the CLK1 and/or CLK2 output pins: D k x 56 kHz D k x 64 kHz D (k x 56 kHz)/8 D (k x 64 kHz)/8 where k can range from 1 to 32. At the SYNC Output pin: D 8kHz The user selects and configures the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. Reverse Mode of Operation When the XRT8000 device is operating in the “Reverse” Mode, it will receive either a 56 kHz or 64 kHz clock signal at the FIN input. From this input signal, the XRT8000 device will synthesize any of the following clock signal frequencies. At the CLK1 and/or CLK2 output pins: D 1.544 MHz D 2.048 MHz D 1.544 MHz/8 = 193 kHz D 2.048 MHz/8 = 256 kHz At the SYNC output pin: D 8 kHz The user can configure the XRT8000 device to generate these clock frequencies by writing the appropriate values into the Command Registers (CR1, CR2, CR3, CR4 and CR5), via the Microprocessor Serial Interface. Note: in the REVERSE mode the contents of CR3 and CR4 has to be all one’s. Slave (Forward, Reverse) Mode of Operation To activate the slave modes of operations the input MSB must be tied low. In these modes an 8kHz signal must be applied to the FIN input in order to obtain output frequencies at T1 or E1 rates. The output frequencies can be selected via the serial interface in a similar fashion as described in the master forward and reverse modes. The Lock Detect Output Pin If both PLL’s are enabled and in locked state then LOCKDET will be active. If one PLL loses lock then LOCKDET will be false. If only one PLL is enabled then only the active PLL will control the state of LOCKDET. |
Similar Part No. - XRT8000_06 |
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Similar Description - XRT8000_06 |
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