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XRT8000 Datasheet(PDF) 11 Page - Exar Corporation |
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XRT8000 Datasheet(HTML) 11 Page - Exar Corporation |
11 / 24 page XRT8000 11 Rev. 1.11 CR3 Register (Power On State = “00000”) SEL14~SEL10: These bits control two parameters: 1.) The frequency multiplier “K” for the PLL1, after selecting Kx56, Kx64 or DATA mode through register CR1 (1 < K < 32), and 2.) The delay time between the rising edge of the sync output signal (Pin 2) and the rising edge of the CLK1 or CLI 2 output signals (See Table 6). Table 4 provides the settings for SEL14~10 bits to generate harmonic of 56kHz, 64kHz or 1.2kHz at the output of PLL1. PLL1 Output Frequency (kHz) SEL14~SEL10 K factor Kx56 MODE Kx64 MODE DATA MODE 00000 1 56 64 1.2 00001 2 112 128 2.4 00010 3 168 192 4.8 00011 4 224 256 7.2 00100 5 280 320 9.6 00101 6 336 384 12 00110 7 392 448 14.4 00111 8 448 512 16.8 01000 9 504 576 19.2 01001 10 560 640 21.6 01010 11 616 704 24 01011 12 672 768 26.4 01100 13 728 832 28.8 01101 14 784 896 31.2 01110 15 840 960 33.6 01111 16 896 1024 36 10000 17 952 1088 38.4 10001 18 1008 1152 40.8 10010 19 1064 1216 43.2 10011 20 1120 1280 43.2 10100 21 1176 1344 43.2 10101 22 1232 1408 43.2 10110 23 1288 1472 43.2 10111 24 1344 1536 43.2 11000 25 1400 1600 43.2 11001 26 1456 1664 43.2 11010 27 1512 1728 43.2 11011 28 1568 1792 43.2 11100 29 1624 1856 43.2 11101 30 1680 1920 43.2 11110 31 1736 1984 43.2 11111 32 1792 2048 43.2 Note: This table applies to forward or slave modes only Table 4. CR3 Register |
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