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SAA4951WP Datasheet(PDF) 11 Page - NXP Semiconductors |
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SAA4951WP Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 25 page  April 1994 11 Philips Semiconductors Preliminary specification Memory controller SAA4951 Table 3 Mode registers. REGISTER BIT NAME REMARKS MODE0 0 (LSB) FSA0 frequency select acquisition bit 0 1 FSA1 frequency select acquisition bit 1 2 FSD0 frequency select display bit 0 3 FSD1 frequency select display bit 1 FSA1 FSA0 acquisition frequency 0 0 12.0 MHz 0 1 13.5 MHz 1 0 16.0 MHz 1 1 18.0 MHz FSD1 FSD0 display frequency 0 0 27.0 MHz 0 1 27.0 MHz 1 0 32.0 MHz 1 1 36.0 MHz 4 FORMAT0 control bit 0 for data format MODE0 5 FORMAT1 control bit 1 for data format FORMAT1 FORMAT0 Y:U:V data rate 0 0 4: 1: 1 0 1 4: 2: 2 1 0 4: 4: 4 1 1 4: 4: 4 6 HDEL0 horizontal delay control bit 0 7 (MSB) HDEL1 horizontal delay control bit 1 the bits HDEL0, HDEL1 control the position of the internal vertical read enable signals for RE1 HDEL1 HDEL0 0 0 2 lines earlier 0 1 1 line earlier 1 0 normal 1 1 1 line later |
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