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SP331 Datasheet(PDF) 8 Page - Sipex Corporation |
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SP331 Datasheet(HTML) 8 Page - Sipex Corporation |
8 / 13 page Date: 03-04-05 Programmable Dual RS-232/RS-485 Transceiver © Copyright 2005 Sipex Corporation 8 THEORY OF OPERATION The SP331 is made up of four separate circuit blocks — the charge pump, drivers, receivers, and decoder. Each of these circuit blocks is described in more detail below. Charge–Pump The charge pump is a Sipex–patented design (U.S. 5,306,954) and uses a unique approach compared to older less efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 10V power supplies. Figure 15(a) shows the waveform found on the positive side of capcitor C2, and Figure 15(b) shows the negative side of capcitor C2. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. Phase 1 — V SS charge storage —During this phase of the clock cycle, the positive side of capacitors C 1 and C2 are initially charged to +5V. Cl + is then switched to ground and charge on C 1 – is transferred to C 2 –. Since C 2 + is connected to FUNCTION TABLE FOR SELECT PINS A B C D MODE FUNCTION 000 0 RS-232 All four RS-232 drivers active 000 1 RS-232 All four RS-232 drivers tri-state 001 0 RS-232 All four RS-232 drivers tri-state 001 1 RS-232 RS-232 (4ch) Loopback 010 0 RS-232/RS-485 T1 and T2 active RS-232; T3 tri-state RS-485 010 1 RS-232/RS-485 T1 and T2 tri-state RS-232; T3 active RS-485 011 0 RS-232/RS-485 T1 and T2 active RS-232; T3 tri-state RS-485 011 1 RS-232/RS-485 RS-232 (2ch) / RS-485 (1ch) Loopback 100 0 RS-485/RS-232 T1 active RS-485; T3 and T4 active RS-232 100 1 RS-485/RS-232 T1 tr-state RS-485; T3 active RS-232; T4 active RS232 101 0 RS-485/RS-232 All RS-485 and RS-232 drivers tri-state 101 1 RS-485/RS-232 RS-485 (1ch) / RS-232 (2ch) Loopback 110 0 RS-485 T1 and T3 active RS-485 110 1 RS-485 T1 tri-state RS-485; T3 active RS-485 111 0 RS-485 T1 active RS-485; T3 tri-state RS-485 111 1 RS-485 RS-485 (2ch) Loopback +5V, the voltage potential across capacitor C 2 is now 10V. Phase 2 — V SS transfer — Phase two of the clock con- nects the negative terminal of C 2 to the VSS storage capacitor and the positive terminal of C 2 to ground, and transfers the generated –l0V to C 3. Simultaneously, the positive side of capaci- tor C 1 is switched to +5V and the negative side is connected to ground. Phase 3 — V DD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C 1 produces –5V in the negative terminal of C 1, which is applied to the negative side of capacitor C 2. Since C2 + is at +5V, the voltage potential across C 2 is l0V. Phase 4 — V DD transfer — The fourth phase of the clock connects the negative terminal of C 2 to ground and transfers the generated l0V across C 2 to C4, the VDD storage capacitor. Again, Table 1. Mode Function Table. (Refer to Control Logic Confirmations for Block Diagrams) |
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