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MGM687

SAA4974H

VARIABLE

Y-DELAY

REFORMATTER

UP-CONVERSION

4 : 1 : 1

TO

4 : 2 : 2

Y-PEAKING

DCTI

UP-CONVERSION

4 : 2 : 2

TO

4 : 4 : 4

BLANKING

SIDEPANELS

OVERLAY

RAM

MICROPROCESSOR

BUS

SNERT-

BUS

I/O

PORT

ROM

YOUT

79

UOUT

76

VOUT

74

4

8

CONTROL

INTERFACE

MEMORY CONTROL

(DISPLAY)

3 to 7

5

10

2

P1.5

to

P1.1

SNRST

13

SNCL

12

SNDA

68

9

HRD

71

HDFL

72

VDFL

66

BLND

63

RE

64

IE2

70

LLD

CONTROL

INTERFACE

MEMORY CONTROL

(ACQUISITION)

24

RSTW

32

WE

47

SWC

33

LLA

22

HA

20

VA

TEST

CONTROL

BLOCK

15

30

TMS

49

TRST

ANATEST

59 to 62

UVI7 to UVI4

51 to 58

YI7 to YI0

SCL

1

SDA

RST

TRIPLE

10-BIT DAC

Fig.1 Block diagram.