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SAA5252P Datasheet(PDF) 11 Page - NXP Semiconductors |
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SAA5252P Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 20 page  1996 Jul 18 11 Philips Semiconductors Product specification Line twenty-one acquisition and display (LITOD) SAA5252 DISPLAY GENERATOR General description The displayed characters are defined on a 5-by-12 matrix within a 7-by-13 window, allowing one blank pixel either side of the character and a blank pixel row above. There are a number of display options available controlled by Register 1, or external pins in ‘stand-alone’ mode. The three display modes are video, text and caption, the device is powered up in the video mode. The display generator reads the Pre-amble Address Code (PAC) then the data associated with that row. Each character is then rounded after which it can be italicized and/or underlined, depending on the PAC or mid-row codes, before being passed on to the output circuitry. Figure 6 shows the character set. Display of external On-Screen Display (OSD) facilities The R, G, B and BLAN outputs of the display have the capability to be put in a 3-state mode allowing other OSD devices to take control of the television R, G, B and BLAN signals. When the BLANIN is held HIGH then the R, G, B and BLAN outputs from display are disabled and the R, G, B and BLAN signals come directly from the RGBIN and BLANIN inputs. This will allow On-Screen Display to be placed on top of the captioning without any corruption, leaving the captions intact when the On-Screen Display is switched off (BLANIN goes LOW). In this form of operation the RGBIN and RGBOUT pins can be considered transparent; BLANIN goes through the normal output buffer to BLAN. Table 1 Register map (WRITE) Table 2 Register map (READ) REGISTER D7 D6 D5 D4 D3 D2 D1 D0 00 DF1/2 RGB, BLAN +ve/ −ve H +ve/ −ve V +ve/ −ve H3 H2 H1 H0 01 CLEAR CH 2/1 NARROW/ WIDE ACQ OFF EN1 EN0 M1 M0 02 −− − − ROW3 ROW2 ROW1 ROW0 03 −− − COL4 COL3 COL2 COL1 COL0 04 − OSD6 OSD5 OSD4 OSD3 OSD2 OSD1 OSD0 REGISTER D7 D6 D5 D4 D3 D2 D1 D0 80 POR 0 0 0 F1/F2 EDS PARITY SHUTDOWN DATA READY 81 PARITY ERROR DATA BIT 7 DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 82 PARITY ERROR DATA BIT 7 DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 |
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