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SAA7130 Datasheet(PDF) 10 Page - NXP Semiconductors |
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SAA7130 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 48 page  2002 Apr 23 10 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL 6.2 Pins grouped by function Table 2 Power supply pins Table 3 PCI interface pins; note 1 SYMBOL PIN TYPE DESCRIPTION VSSA 97, 108, 113 and 119 AG analog ground for integrated analog signal processing VDDA 95, 110 and 115 AS analog supply voltage for integrated analog signal processing VSSD 20, 39, 55, 64, 74, 93 and 128 VG digital ground for digital circuit, core and I/Os VDDD 1, 19, 38, 54, 65, 73 and 92 VS digital supply voltage for digital circuit, core and I/Os SYMBOL PIN TYPE DESCRIPTION PCI_CLK 40 PI PCI clock input: reference for all bus transactions, up to 33.33 MHz PCI_RST# 127 PI PCI reset input: will 3-state all PCI pins (active LOW) AD31 to AD0 4 to 11, 14 to 18, 21 to 23, 34 to 37, 41 to 44 and 46 to 53 PIO and T/S multiplexed address and data input or output: bi-directional, 3-state CBE3# to CBE0# 12, 24, 33 and 45 PIO and T/S command code input or output: indicates type of requested transaction and byte enable, for byte aligned transactions (active LOW) PAR 32 PIO and T/S parity input or output: driven by the data source, even parity over all pins AD and CBE# FRAME# 25 PIO and S/T/S frame input or output: driven by the current bus master (owner), to indicate the beginning and duration of a bus transaction (active LOW) TRDY# 27 PIO and S/T/S target ready input or output: driven by the addressed target, to indicate readiness for requested transaction (active LOW) IRDY# 26 PIO and S/T/S initiator ready input or output: driven by the initiator, to indicate readiness to continue transaction (active LOW) STOP# 29 PIO and S/T/S stop input or output: target is requesting the master to stop the current transaction (active LOW) IDSEL 13 PI initialization device select input: this input is used to select the SAA7130HL during configuration read and write transactions DEVSEL# 28 PIO and S/T/S device select input or output: driven by the target device, to acknowledge address decoding (active LOW) REQ# 3 PO PCI request output: the SAA7130HL requests master access to PCI-bus (active LOW) GNT# 2 PI PCI grant input: the SAA7130HL is granted to master access PCI-bus (active LOW) |
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