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SAA7185WP Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA7185WP Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 36 page  1996 Jul 08 8 Philips Semiconductors Preliminary specification Digital Video Encoder (DENC2) SAA7185 Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y/C output. For transfer characteristics of the chrominance interpolation filter see Figs 3 and 4. The amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or Extended Data Service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 Ω. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. Output Interface In the output interface encoded Y and C signals are converted from digital-to-analog in 10-bit resolution both Y and C signals are combined to a 10-bit CVBS signal, also; in front of the summation point, the luminance signal can optionally be fed through a further filter stage, suppressing components in the range of subcarrier frequency. Thus, a type of Cross Colour reduction is provided, which is useful in a standard TV set with CVBS input. Slopes of synchronization pulses are not affected with any Cross Colour reduction active. Three different filter characteristics or bypass are available, see Fig.5. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 15 ⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of all DACs can be set together via software control to minimum output voltage for either purpose. Synchronization The synchronization of the DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to the video signal on VP (and DP, if used) can be influenced by programming the polarity and on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. If the horizontal phase is not be influenced by RCV1, a horizontal pulse needs to be supplied at the RCV2 pin. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of DENC2 runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the IC can output: • A Vertical Sync signal (VS) with 3 or 2.5 lines duration, or • An ODD/EVEN signal which is LOW in odd fields, or • A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 fields. On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up e.g. a composite blanking signal. The phase of the pulses output on RCV1 or RCV2 are referenced to the VP port, polarity of both signals is selectable. |
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