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SAA7196 Datasheet(PDF) 7 Page - NXP Semiconductors

Part # SAA7196
Description  Digital video decoder, Scaler and Clock generator circuit DESCPro
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA7196 Datasheet(HTML) 7 Page - NXP Semiconductors

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1996 Nov 04
7
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
SAA7196
6
PINNING
SYMBOL
PIN
STATUS
DESCRIPTION
XTAL
1
O
26.8 MHz crystal oscillator output, not used if TTL clock signal is used
XTALI
2
I
26.8 MHz crystal oscillator input or external clock input (TTL, square wave)
SDA
3
I/O
I2C-bus data line
SCL
4
I
I2C-bus clock line
I2CSA
5
I
I2C-bus set address
CHR0
6
I
digital chrominance input signal (bit 0)
CHR1
7
I
digital chrominance input signal (bit 1)
CHR2
8
I
digital chrominance input signal (bit 2)
CHR3
9
I
digital chrominance input signal (bit 3)
CHR4
10
I
digital chrominance input signal (bit 4)
CHR5
11
I
digital chrominance input signal (bit 5)
CHR6
12
I
digital chrominance input signal (bit 6)
CHR7
13
I
digital chrominance input signal (bit 7)
VDDD1
14
+5 V digital supply voltage 1
CTST
15
connected to ground (clock test pin)
VSSD1
16
digital ground 1 (0 V)
CVBS0
17
I
digital CVBS input signal (bit 0)
CVBS1
18
I
digital CVBS input signal (bit 1)
CVBS2
19
I
digital CVBS input signal (bit 2)
CVBS3
20
I
digital CVBS input signal (bit 3)
CVBS4
21
I
digital CVBS input signal (bit 4)
CVBS5
22
I
digital CVBS input signal (bit 5)
CVBS6
23
I
digital CVBS input signal (bit 6)
CVBS7
24
I
digital CVBS input signal (bit 7)
HSY
25
O
horizontal sync indicator output (programmable)
HCL
26
O
horizontal clamping pulse output (programmable)
VDDA
27
+5 V analog supply voltage
LFCO
28
O
line frequency control output signal to CGC
(multiple of present line frequency)
VSSA
29
analog ground (0 V)
VSSD2
30
digital ground 2 (0 V)
VDDD2
31
+5 V digital supply voltage 2
GPSW2
32
O
general purpose output 2 (controllable via I2C-bus)
GPSW1
33
O
general purpose output 1 (controllable via I2C-bus)
RTS1
34
O
real time status output 1; controlled by bit RTSE
RTS0
35
O
real time status output 0; controlled by bit RTSE
RES
36
O
reset output, active LOW
CGCE
37
I
enable input for internal CGC (connected to +5 V)
CREF
38
O
clock qualifier output (test only)


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