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SAA8115HL Datasheet(PDF) 6 Page - NXP Semiconductors

Part # SAA8115HL
Description  Digital camera USB interface
Download  56 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SAA8115HL Datasheet(HTML) 6 Page - NXP Semiconductors

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2000 Jan 27
6
Philips Semiconductors
Preliminary specification
Digital camera USB interface
SAA8115HL
7
PINNING
SYMBOL
PIN
TYPE(1)
DESCRIPTION
C3
1
O
horizontal CCD transfer pulse output
C2
2
O
horizontal CCD transfer pulse output (FH1)
C1
3
O
horizontal CCD transfer pulse output (FH2)
C4
4
O
horizontal CCD transfer pulse output
SHUTTER
5
O
shutter control output for CCD charge reset
GND1
6
P
ground 1 for output buffers
VDD1
7
P
supply voltage 1 for output buffers
RG
8
O
reset output for CCD output amplifier gate
FS
9
O
data sample-and-hold pulse output to TDA8784/87 (SHD)
FCDS
10
O
preset sample-and-hold pulse output to TDA8784/87 (SHP)
CLK1
11
O
pixel clock to TDA8784/87 and SAA8112HL
DCP
12
O
dummy clamp pulse output to TDA8784/87
BCP
13
O
optical black clamp pulse output to TDA8784/87
VD
14
O
vertical definition pulse to SAA8112HL
HD
15
O
horizontal definition pulse to SAA8112HL
VDD2
16
P
supply voltage 2 for output buffers
CLK2
17
O
double pixel clock to SAA8112HL
GND2
18
P
ground 2 for output buffers
YUV0
19
I
multiplexed YUV bit 0
YUV1
20
I
multiplexed YUV bit 1
YUV2
21
I
multiplexed YUV bit 2
YUV3
22
I
multiplexed YUV bit 3
DGND1
23
P
digital ground 1 for input buffers, predrivers and for the digital core
VDDD1
24
P
digital supply voltage 1 for input buffers, predrivers and one part of the digital
core
YUV4
25
I
multiplexed YUV bit 4
YUV5
26
I
multiplexed YUV bit 5
YUV6
27
I
multiplexed YUV bit 6
YUV7
28
I
multiplexed YUV bit 7
DGND2
29
P
digital ground 2 for input buffers, predrivers and for the digital core
LLC
30
I
line-locked clock input (delayed CLK2) for YUV-port from SAA8112HL
HREF
31
I
horizontal reference input for YUV-port from SAA8112HL
VS
32
I
vertical synchronization input for YUV-port from SAA8112HL
RESET
33
I
Power-on reset input (for video processing and PPG)
SNDA
34
I/O
data input/output for SNERT-interface (communication between SAA8115HL
and SAA8112HL)
SNCL
35
I
clock input for SNERT-interface (communication between SAA8115HL and
SAA8112HL)
SNRES
36
I
reset input for SNERT-interface (communication between SAA8115HL and
SAA8112HL)


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