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MAX4924ELT+ Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX4924ELT+ Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 7 page Overvoltage Protectors with External pFET 4 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1IN Voltage Input. IN is both the power-supply input and the overvoltage/undervoltage sense input. Bypass IN to GND with a 1µF ceramic capacitor as close as possible to the device to enable ±15kV (HBM) ESD protection on IN. 2 GND Ground 3 FLAG Fault Indication Open-Drain Output. FLAG deasserts high during undervoltage and overvoltage lockout conditions. FLAG asserts low during normal operation. 4 GATE pFET Gate Drive Output. GATE is driven high during a fault condition to turn off the external pFET. When VUVLO < VIN < VOVLO, GATE is driven low and the external pFET is turned on. 5, 6 N.C. No Connection. Not internally connected. Leave N.C. unconnected. MAX4923–MAX4926 GATE DRIVER GATE IN GND FLAG CONTROL LOGIC AND TIMER OVLO AND UVLO DETECTOR Functional Diagram VIN tDEB tDEB VOVLO VUVLO 3V tGON tGON tFLAG tFLAG tGOFF tGOFF O.5V VIN - 0.5V VIN - 0.5V O.5V VGATE VFLAG Figure 1. Timing Diagram |
Similar Part No. - MAX4924ELT+ |
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Similar Description - MAX4924ELT+ |
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