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SC4000 Datasheet(PDF) 10 Page - NXP Semiconductors |
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SC4000 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 52 page 2000 Sep 07 10 Philips Semiconductors Preliminary specification Universal Timeslot Interchange SC4000 PIN DESCRIPTION Pin Name Input/Output Pin Number Pin Description D_[7:0] I/O 44,43,42,40, 39,38,36,35 (TTL Bi-directional) Microprocessor Data Bus. These bi-directional, tri-state lines allow the microprocessor to access SC4000 internal registers as well as the source/destination routing memory and parallel access registers. A_[8:0] I 34,32,31,30, 28,27,26,25,24 (TTL Input) Microprocessor Address Bus. These inputs select the internal registers used by a read or write opera- tion. Normally these inputs are connected to Microprocessor address lines A[8:0]. ALE I 22 (TTL Input) Address Latch Enable. This input pin is tied to high in non-multiplexed mode. Otherwise, in multi- plexed mode, the Microprocessor Address Bus is latched internally on the falling edge of this signal. CS_1_N I 17 (TTL Input) Chip Select 1. Reserved for future internal HDLC controller. If unused, this pin should be connected to high. CS_0_N I 16 (TTL Input) Chip Select 0. This active low signal selects the SC4000 for a microprocessor read or write operation. I_N or M I 12 (TTL Input) Microprocessor Bus Interface Mode Select. When this input is low, Intel Bus Mode (I_N) is selected. When this input is high, Motorola Bus (M) Mode is selected. RD_N or STRB_N I 19 (TTL Input) In Intel Bus Mode (RD_N), this active low input operates with CS_0_N to configure the data bus lines D_[7:0] as output. In Motorola Bus Mode (STRB_N), this active low input operates with CS_0_N to enable a read or write operation. WR_N or R/W_N I 20 (TTL Input) In Intel Bus Mode (WR_N), when CS_0_N is active, the rising edge of WR_N is used to latch an inter- nal data register with data provided via the data bus lines D_[7:0]. In Motorola Bus Mode (R/W_N), this R/W_N input is used to distinguish between read or write during a microprocessor access. DACK_N I 21 (TTL Input, Pull up) DMA Acknowledge Reserved for future internal HDLC controller. If unused, this pin should be left unconnected RESET I 96 (TTL Input) Reset. This active high signal initializes the microprocessor interface, configuration, routing and paral- lel access registers. X_IN I 2 (CMOS Input) Crystal Clock Input. This pin is a CMOS level input of either 2.048, 4.096, 8.192, 16.384, 32.768 or 65.536 MHz. A crystal of 16.384 MHz from X_IN to X_OUT may also be used. X_OUT O 1 (CMOS Output) Crystal Clock Output. REF_8K_3 or REF_8K_OUT I O 7 (TTL Bi-Directional) Internal Master PLL (REF_8K_3). If configuration register bit C_43=0, this pin is a Local 8 KHz Reference 3 Input. External Master PLL (REF_8K_OUT). If configuration register bit C_43=1, this pin is an 8 KHz Reference Output. REF_8K_2 or CLK_IN I 6 (TTL Input) Internal Master PLL (REF_8K_2). If configuration register bit C_43=0, this pin is a Local 8 KHz Refer- ence 2 Input. External Master PLL (CLK_IN). If configuration register bit C_43=1, this is a clock input from external master PLL. REF_8K_1 I 5 (TTL Input) Local 8 KHz Reference 1 Input. REF_8K_0 I 4 (TTL Input) Local 8 KHz Reference 0 Input. SI_[3:0] I 95,94,92,91 (TTL Input, Pull Up) Local Bus Serial Input Data Streams. This pin can be programmed to 2.048, 4.096 or 8.192 Mb/s data rates. TXD_0 I 9 (TTL Input, Pull Up) Message Channel Transmit Data. This pin is for the SCbus Message channel transmit data input line. TEST I 98 (TTL Input) NAND Gate Test Mode Enable. When in test mode (TEST=1) each pin except VDD/VSS/X_OUT is nanded with the preceding pin and output at both DRQ_R and DRQ_T pins. INT_1 I/O 15 (TTL Bi-directional) Interrupt Request 1. Reserved for future internal HDLC controller. If unused, this pin should be left unconnected. INT_0 I/O 14 (TTL Bi-directional) Interrupt Request 0. This pin will be asserted (controlled by C_[55:53]) if either SCbus Error, SCbus CLKFAIL, Frame Boundary or Internal Master PLL Error and INT_0 unmasked (C_53 = 1). |
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