Quad, Low-Power, 500Mbps

ATE Driver/Comparator

8

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Note 1:

All MIN and MAX limits are 100% tested in production.

Note 2:

≥ 10MΩ. The applicable supply currents are measured with typical supply

voltages.

Note 3:

Does not include internal dissipation of the comparator outputs. With output loads of 50

240mW (typ) to the total chip power (MAX996_ _HCCQ, MAX996_ _JCCQ).

Note 4:

Externally forced voltages may exceed this range provided that the absolute maximum ratings are not exceeded.

Note 5:

Transition time from LLEAK being asserted to leakage current dropping below specified limits.

Note 6:

Transition time from LLEAK being deasserted to output returning to normal operating mode.

Note 7:

Based on simulation results only.

Note 8:

With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.

Note 9:

Relative to straight line between 0 and 3V.

Note 10: Full ranges are -1.3V

Note 11: Nominal target value is 50

Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.

Ω. External signal driven into T-line is a 0 to 3V edge with 1.2ns rise time (10% to 90%).

Measurement is made using the comparator.

Note 13: Measured from the crossing point of DATA_ inputs to the settling of the driver output.

Note 14: Prop delays are measured from the crossing point of the differential input signals to the 50% point of expected output

swing. Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%).

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Voltage Gain

0.96

1.00

V/V

Voltage-Gain Temperature

Coefficient

-100

ppm/

°C

to 6.5V

±10

Clamp Linearity

to 5.3V

±10

mV

50

95

Short-Circuit Output Current

-95

-50

mA

50

55

Clamp DC Impedance

50

55

Ω

ELECTRICAL CHARACTERISTICS (continued)