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S29NS256PABBJW000 Datasheet(PDF) 5 Page - SPANSION |
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S29NS256PABBJW000 Datasheet(HTML) 5 Page - SPANSION |
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5 / 86 page  February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 5 Da ta Sh e e t (Adv a n ce In f o r m ation) Figures Figure 3.1 Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10 Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11 Figure 4.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11 Figure 4.4 VDD064—64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P . . . . . . . . . . . . . . . . . . 12 Figure 4.5 VDE044—44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13 Figure 6.1 Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6.2 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6.3 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 6.4 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 6.5 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 7.1 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 7.2 PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 7.3 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 10.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 10.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 10.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 10.4 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 10.5 VCC Power-Up Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 10.6 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 10.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 68 Figure 10.8 8-Word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . 69 Figure 10.9 Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 10.10 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 10.11 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 10.12 Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 10.13 Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 10.14 Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 10.15 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 10.16 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10.18 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10.19 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10.20 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 10.21 Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 |
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