Philips Semiconductors

Product specification

SCC2692

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

11

Table 1.

SCC2692 Register Addressing

A3

A2

A1

A0

READ (RDN = 0)

WRITE (WRN = 0)

0

0

0

0

Mode Register A (MR1A, MR2A)

Mode Register A (MR1A, MR2A)

0

0

0

1

Status Register A (SRA)

Clock Select Register A (CSRA)

0

0

1

0

BRG Test

Command Register A (CRA)

0

0

1

1

Rx Holding Register A (RHRA)

Tx Holding Register A (THRA)

0

1

0

0

Input Port Change Register (IPCR)

Aux. Control Register (ACR)

0

1

0

1

Interrupt Status Register (ISR)

Interrupt Mask Register (IMR)

0

1

1

0

Counter/Timer Upper Value (CTU)

C/T Upper Preset Value (CRUR)

0

1

1

1

Counter/Timer Lower Value (CTL)

C/T Lower Preset Value (CTLR)

1

0

0

0

Mode Register B (MR1B, MR2B)

Mode Register B (MR1B, MR2B)

1

0

0

1

Status Register B (SRB)

Clock Select Register B (CSRB)

1

0

1

0

1X/16X Test

Command Register B (CRB)

1

0

1

1

Rx Holding Register B (RHRB)

Tx Holding Register B (THRB)

1

1

0

0

Reserved

Reserved

1

1

0

1

Input Ports IP0 to IP6

Output Port Conf. Register (OPCR)

1

1

1

0

Start Counter Command

Set Output Port Bits Command

1

1

1

1

Stop Counter Command

Reset Output Port Bits Command

* See Table 6 for BRG Test frequencies in this data sheet, and

“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,

SCC68681 and SCC2698B” in application notes elsewhere in this publication

Table 2.

Register Bit Formats

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR1A

RxRTS

CONTROL

RxINT

SELECT

ERROR

MODE*

PARITY MODE

PARITY

TYPE

BITS PER

CHARACTER

MR1A

MR1B

0 = No

1 = Yes

0 = RxRDY

1 = FFULL

0 = Char

1 = Block

00 = With Parity

01 = Force Parity

10 = No Parity

11 = Multidrop Mode

0 = Even

1 = Odd

00 = 5

01 = 6

10 = 7

11 = 8

NOTE:

*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR2A

CHANNEL MODE

TxRTS

CONTROL

CTS

ENABLE Tx

STOP BIT LENGTH*

MR2A

MR2B

00 = Normal

01 = Auto-Echo

10 = Local loop

11 = Remote loop

0 = No

1 = Yes

0 = No

1 = Yes

0 = 0.563

4 = 0.813

8 = 1.563

C = 1.813

1 = 0.625

5 = 0.875

9 = 1.625

D = 1.875

2 = 0.688

6 = 0.938

A = 1.688

E = 1.938

3 = 0.750

7 = 1.000

B = 1.750

F = 2.000

NOTE: *Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.

CSRA

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CSRA

CSRB

RECEIVER CLOCK SELECT

TRANSMITTER CLOCK SELECT

CSRB

See Text

See Text

* See Table 6 for BRG Test frequencies in this data sheet, and

“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,

SCC68681 and SCC2698B” in application notes elsewhere in this publication

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CRA

CRB

MISCELLANEOUS COMMANDS

DISABLE Tx

ENABLE Tx

DISABLE Rx

ENABLE Rx

CRB

See Text and Timing Requirement

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.