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AK93C10AF Datasheet(PDF) 5 Page - Asahi Kasei Microsystems |
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AK93C10AF Datasheet(HTML) 5 Page - Asahi Kasei Microsystems |
5 / 13 page ASAHI KASEI [AK93C85A/95A/10A] DAM02E-03 2004/05 - 5 - WRITE The write instruction is followed by 16 bits of data to be written into the specified address. AK93C85A: After the last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of 250ns (Tcs). AK93C95A/10A: The self-timed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the self-timed programming cycle is initiated. The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part. DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the address specified in the instruction has been written with the new data pattern contained in the instruction and the part is ready for a next instruction. WRITE (AK93C85A) WRITE (AK93C95A) WRITE (AK93C10A) 17 Busy 16 Hi-Z 0 tE/W CS SK DI DO Start Bit Op code Ready AK93C10A output a logic "1" (Ready status), if previous instruction is WRITE. D0 1 2 3 4 5 1415 293031 D1 D2 D14 D15 A0 A1 A10 1 0 1 0 A11 Busy 16 Hi-Z 0 tE/W CS SK DI DO Start Bit Op code Ready AK93C95A output a logic "1" (Ready status), if previous instruction is WRITE. D0 1 2 3 4 5 1415 282930 D1 D2 D14 D15 A0 A1 A9 1 0 1 0 A10 13 Hi-Z 0 tE/W CS SK DI DO Start Bit Op code tCS Busy Ready AK93C85A output a logic "1" (Ready status), if previous instruction is WRITE. D0 1 2 3 4 5 1415 272829 D1 D2 D14 D15 A0 A1 A8 1 0 1 0 A9 12 13 |
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