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AK6510C Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK6510C Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
8 / 18 page ASAHI KASEI [AK6514C] DAP04E-00 2005/03 - 8 - WRSR (WRITE STATUS REGISTER) The WRSR instruction can set the Write Protect Block size of the memory array. AK6514C has 4 Blocks of memory arrays. Write Protect Block size can be selected from 1/4, 1/2 and whole memory array. The block, which is set by Write Protect, is Read only. BP0 bit, BP1 bit, and WPEN bit are programmable with EEPROM memory cell bits. The characteristics of those bits (WREN, tE/W, RDSR) are same as the EEPROM memory array. WP pin function can be set by WPEN (WRITE PROTECT ENABLE) bit which is defined by WRSR function. When WP pin is low level and WPEN bit is "1", the WRITE function to Status register, which has WPEN bit and BP0/BP1 bit, and to Write Disable Block is not performed. Then WRITE function is performed only to the Write enable block. When WP pin is "1" or WPEN bit is "0", then the function of WP pin is disabled and WRITE function to the Status Register is performed. WREN function should be done before WRSR function. And after the Programming function, AK6514C becomes Write Disable status automatically. WRSR WPEN Bit WP Pin WEN Bit Write Protected Block Not Protected Block Status Register 0 X 0 WRITE Disable WRITE Disable WRITE Disable 0 X 1 WRITE Disable WRITE Enable WRITE Enable 1 Low 0 WRITE Disable WRITE Disable WRITE Disable 1 Low 1 WRITE Disable WRITE Enable WRITE Disable X High 0 WRITE Disable WRITE Disable WRITE Disable X High 1 WRITE Disable WRITE Enable WRITE Enable Table 3. WPEN function Status Register bits BP1 BP0 Write Protected Block 0 0 none 0 1 3000h - 3FFFh 1 0 2000h - 3FFFh 1 1 0000h - 3FFFh Table 4. Write Protected Block Size Hi-Z 0123456789 10 11 12 13 14 15 0 0 0 0 00 1 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 CS SCK SI SO X = don’t care X |
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