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AK5380VT Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AK5380VT Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
3 / 17 page ASAHI KASEI [AK5380] MS0100-E-01 2001/7 - 3 - PIN/FUNCTION No. Pin Name I/O Description 1 AINR I Rch Analog Input Pin 2 AINL I Lch Analog Input Pin 3 NC - NC Pin No internal bonding. 4 VCOM O Common Voltage Output Pin Normally connected to AGND with a 0.1 µF ceramic capacitor in parallel with an electrolytic capacitor less than 2.2 µF. 5 AGND - Analog Ground Pin, 0V 6 VA - Analog Power Supply Pin, +4.5 ∼+5.5V 7 VD - Digital Power Supply Pin, +2.7 ∼+5.5V(fs=48kHz), +4.5∼+5.5V(fs=96kHz) 8 DGND - Digital Ground Pin, 0V 9 SDTO O Serial Data Output Pin Data bits are presented MSB first, in 2’s complement format. This pin is “L” in the power-down mode. 10 LRCK I Left/Right Channel Select Pin The fs clock is input to this pin. 11 MCLK I Master Clock Input Pin 12 SCLK I Serial Data Input Pin Output data is clocked out on the falling edge of SCLK. 13 PDN I Power-Down Pin When “L”, the circuit is in power-down mode. The AK5380 should always be reset upon power-up. 14 DIF I Serial Interface Format Pin “L”: MSB justified, “H”: I 2S 15 TTL I Digital Input Level Select Pin “L”: CMOS level (VD=2.7 ∼5.5V), “H”: TTL level (VD=4.5∼5.5V) 16 TST I Test Pin (Internal pull-down pin) This pin should be left open. Note: All input pins except pull-down pins should not be left floating. |
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