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SST32HF402-70-4E-L3K Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc

Part # SST32HF402-70-4E-L3K
Description  Multi-Purpose Flash (MPF) SRAM ComboMemory
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST32HF402-70-4E-L3K Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc

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Data Sheet
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
3
©2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST32HF202/402/
802. SDP commands are loaded to the flash memory bank
using standard microprocessor Write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
Flash Word-Program Operation
The flash memory bank of the SST32HF202/402/802
devices is programmed on a word-by-word basis. Before
Program operations, the memory must be erased first. The
Program operation consists of three steps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load word address
and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either BEF# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either BEF# or WE#, whichever occurs first. The
third step is the internal Program operation which is initiated
after the rising edge of the fourth WE# or BEF#, whichever
occurs first.
The Program operation, once initiated, will be completed,
within 20 µs. See Figures 7 and 8 for WE# and BEF# con-
trolled Program operation timing diagrams and Figure 18 for
flowcharts. During the Program operation, the only valid
flash Read operations are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any SDP commands loaded dur-
ing the internal Program operation will be ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF202/402/802 offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle.
The address lines A16-A11, for SST32HF202, A17-A11, for
SST32HF402, and A18-A11, for SST32HF802, are used to
determine the sector address. The Block-Erase operation
is initiated by executing a six-byte command sequence with
Block-Erase command (50H) and block address (BA) in
the last bus cycle. The address lines A16-A15, for
SST32HF202, A17-A15, for SST32HF402, and A18-A15, for
SST32HF802, are used to determine the block address.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase operation can be determined using
either Data# Polling or Toggle Bit methods. See Figures 12
and 13 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Flash Chip-Erase Operation
The SST32HF202/402/802 provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 10 for timing diagram,
and Figure 21 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF202/402/802 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.


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