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SST32HF32A2 Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST32HF32A2 Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 35 page Preliminary Specifications Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A2 5 ©2005 Silicon Storage Technology, Inc. S71261-01-000 5/05 Hardware Block Protection The SST32HF32A2 support top hardware block protection, which protects the top 32 KWord block of the device. The Boot Block address is 1F8000H-1FFFFFH. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 17). The Erase or Program operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. Flash Software Data Protection (SDP) The SST32HF32A2 provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Pro- gram operation requires the inclusion of a series of three- byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF32A2 devices are shipped with the software data protection per- manently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. PSRAM Read The PSRAM Read operation of the SST32HF32A2 is con- trolled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the out- puts. BES1# and BES2 are used for PSRAM bank selec- tion. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. PSRAM Write The PSRAM Write operation of the SST32HF32A2 is con- trolled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the PSRAM. During the Word-Write operation, the addresses and data are ref- erenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. Product Identification The Product Identification mode identifies the devices as the SST32HF32A2 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and PSRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multi- ple manufacturers in the same socket. For details, see Tables 4 and 5 for software operation, Figure 14 for the software ID entry and read timing diagram and Figure 23 for the ID entry command sequence flowchart. TABLE 2: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST32HF32A2 0001H 235AH T2.1 1261 |
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