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SST39SF040-70-4I-WH Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST39SF040-70-4I-WH Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
9 / 24 page Data Sheet 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 9 ©2003 Silicon Storage Technology, Inc. S71147-06-000 8/04 AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V Symbol Parameter SST39SF010A/020A/040-45 SST39SF010A/020A/040-70 Units Min Max Min Max TRC Read Cycle Time 45 70 ns TCE Chip Enable Access Time 45 70 ns TAA Address Access Time 45 70 ns TOE Output Enable Access Time 25 35 ns TCLZ1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. CE# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns TCHZ1 CE# High to High-Z Output 15 25 ns TOHZ1 OE# High to High-Z Output 15 25 ns TOH1 Output Hold from Address Change 0 0 ns T9.4 1147 TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Byte-Program Time 20 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns TDH1 Data Hold Time 0 ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms T10.1 1147 |
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