 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SST34HF324G-70-4E-L3KE Datasheet(PDF) 4 Page - Silicon Storage Technology, Inc |
|
||||||||||||||||||||||||||||||
SST34HF324G-70-4E-L3KE Datasheet(HTML) 4 Page - Silicon Storage Technology, Inc |
|
|
4 / 30 page  4 Data Sheet 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G ©2006 Silicon Storage Technology, Inc. S71310-00-000 6/06 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. Data Protection The SST34HF324G provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Hardware Block Protection The SST34HF324G provide a hardware block protection which protects the outermost 8 KWord in Bank 1. The block is protected when WP# is held low. See Figure 3 for Block- Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 17). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 16). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 16 and 17 for timing diagrams. Software Data Protection (SDP) The SST34HF324G provide the JEDEC standard Soft- ware Data Protection scheme for all data alteration opera- tions, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF324G are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15- DQ8 are “Don’t Care” during any SDP command sequence. TABLE 1: Write Operation Status Status DQ7 DQ6 DQ2 Normal Operation Standard Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Erase- Suspend Mode Read From Erase Suspended Sector/ Block 1 1 Toggle Read From Non-Erase Suspended Sector/ Block Data Data Data Program DQ7# Toggle No Toggle T1.0 1310 |
Similar Part No. - SST34HF324G-70-4E-L3KE |
|
Similar Description - SST34HF324G-70-4E-L3KE |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
