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SST55LC100M-45-I-TQWE Datasheet(PDF) 11 Page - Silicon Storage Technology, Inc |
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SST55LC100M-45-I-TQWE Datasheet(HTML) 11 Page - Silicon Storage Technology, Inc |
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11 / 75 page  Advance Information CompactFlash Card Controller SST55LC100M ©2006 Silicon Storage Technology, Inc. S71316-00-000 3/06 11 IORD# (Memory Card mode) 19 F1 I I3U This signal is not used in this mode. IORD# (PC Card I/O mode) This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash card when the card is configured to use the I/O interface. IORD# (True IDE mode) In True IDE mode, this signal has the same function as in PC card I/O mode. IOWR# (Memory Card mode) 57 H9 I I3U This signal is not used in this mode. IOWR# (PC Card I/O mode) The I/O Write strobe pulse is used to clock I/O data on the card data bus into the CompactFlash card controller registers when the CompactFlash card is configured to use the I/O interface. IOWR# (True IDE mode) In True IDE mode, this signal has the same function as in PC Card I/O mode. OE# (Memory Card mode) 13 D1 I I3U This is an Output Enable strobe generated by the host inter- face. It is used to read data from the CompactFlash card in Memory mode and to read the CIS and configuration registers. OE# (PC Card I/O mode) In PC Card I/O mode, this signal is used to read the CIS and configuration registers. ATASEL# (True IDE mode) To enable True IDE mode this input should be grounded by the host. Ready (Memory Card mode) 21 G1 O O1 In Memory mode this signal is set high when the Compact- Flash card is ready to accept a new data transfer operation and held low when the card is busy. At power up and at Reset, the Ready signal is held low (busy) until the CompactFlash card has completed its power up or reset function. No access of any type should be made to the CompactFlash card during this time. IREQ# (PC Card I/O mode) I/O Operation - After the CompactFlash card has been config- ured for I/O operation, this signal is used as Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. INTRQ (True IDE mode) In True IDE mode signal is the active high Interrupt Request to the host. REG# (Memory Card mode) 20 G2 I I3U This signal is used during Memory cycles to distinguish between Common Memory and Register (Attribute) Memory Attribute Memory Select accesses. High for Common Memory, Low for Attribute Memory. REG# (PC Card I/O mode) The signal must also be active (low) during I/O Cycles when the I/O address is on the Bus. Reserved (True IDE mode) In True IDE mode this input signal is not used and should be connected to VDD by the host. TABLE 3-1:Pin Assignments (Continued) (3 of 6) Signal Name 100-lead 84-ball Pin Type I/O Type1 Name and Functions |
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