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SST79LF008-33-C-LRRF Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc

Part # SST79LF008-33-C-LRRF
Description  Mobile Platform Controller plus 8 Mbit LPC Firmware Flash
Download  252 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST79LF008-33-C-LRRF Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc

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Advance Information
Mobile Platform Controller
8 Mbit LPC Firmware Flash
SST79LF008
©2006 Silicon Storage Technology, Inc.
S71320-01-000
10/06
FIGURE 11-1: Framing Error Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
FIGURE 11-2: UART Timings in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
FIGURE 11-3: UART Timings in Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
FIGURE 12-1: SPI Master-Slave Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
FIGURE 12-2: SPI Transfer Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
FIGURE 12-3: SPI Transfer Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
FIGURE 13-1: SMBus Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
FIGURE 13-2: SMBus Relationship of SDAn to SCLn for Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
FIGURE 13-3: SMBus Byte Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
FIGURE 13-4: SMBus Address Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
FIGURE 13-5: SMBus Master Transmit Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
FIGURE 13-6: SMBus Master Receive Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
FIGURE 13-7: SMBus Slave Transmit Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
FIGURE 13-8: SMBus Slave Receive Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
FIGURE 13-9: SMBus Transmit/Receive Mode Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
FIGURE 14-1: PS/2 Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
FIGURE 14-2: PS/2 Receive Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
FIGURE 14-3: PS/2 Transmit Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
FIGURE 15-1: Fan Tachometer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
FIGURE 16-1: ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
FIGURE 16-2: Example of ADC Operation (Single Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
FIGURE 16-3: Example of ADC Operation (Continuous Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
FIGURE 17-1: DAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
FIGURE 18-1: KBC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
FIGURE 19-1: GA20 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
FIGURE 19-2: : Host and 8051 Control of GA20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
FIGURE 20-1: SCI and SMI Generation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
FIGURE 22-1: Serialized IRQ cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
FIGURE 24-1: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
FIGURE 24-2: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
FIGURE 24-3: LCLK Wave Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
FIGURE 24-4: LPC Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
FIGURE 24-5: LPC Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
FIGURE 24-6: LPC Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
FIGURE 24-7: External Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
FIGURE 24-8: External Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
FIGURE 24-9: Power Up and External Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
FIGURE 24-10: SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
FIGURE 24-11: PS/2 Hardware State Machine Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 240
FIGURE 24-12: PS/2 Hardware State Machine Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 240
FIGURE 24-13: PS/2 Interrupt Timing in bit-banging mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
FIGURE 24-14: UART Timing Diagram (Shift Register Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
FIGURE 24-15: SPI Master Timing Diagram (CPHA=0, MSTR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245


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