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MH64S72QJA-7 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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MH64S72QJA-7 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
1 / 56 page MITSUBISHI ELECTRIC 4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH64S72QJA -7,-8 MITSUBISHI LSIs 16/Jun./1999 MIT-DS-0332-0.0 DESCRIPTION APPLICATION Main memoryunit for computers, Microcomputer memory. FEATURES Type name 100MHz 6ns 6ns MH64S72QJA-8 MH64S72QJA-7 Utilizes industry standard 32M X 4 Synchronous DRAMs in TSOP package , industry standard Resister in TSSOP package , and industrystandard PLL in TSSOP package. Single 3.3V +/- 0.3V power supply LVTTL Interface 4096 refresh cycles every64ms Max. Frequency CLK Access Time [latch mode] (CL = 4) 100MHz PRELIMINARY Some of contents are subject to change w ithout notice. 6ns 6ns CLK Access Time [buffer mode] (CL = 3) 1 1pin 10pin 11pin 40pin 41pin 84pin 85pin 94pin 95pin 124pin 125pin 168pin The MH64S72QJA is 67108864 - word x 72-bit Sy nchronous DRAM stacked structural module. This consist of thirty -six industry st andard 32M x 4 Sy nchronous DRAMs in TSOP. The stacked structure of TSOP on a card edge dual in- line package prov ides any application where high densities and large of quantities memory are required. This is a socket-ty pe memory m odule ,suitable f or easy interchange or addition of module. |
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