Fact Sheet

All-in-OneMemory

SST88VP1107

9

©2007 Silicon Storage Technology, Inc.

S71354(01)-00-000

07/07

Debug Interface

SCICLK

J7

I (PD)

I_PD1

Serial Interface Clock Input

DNU

G5

-

-

Do not use. Reserved

DNU

K8

-

-

Do not use. Reserved

SCIDI

H8

I (PU)

I_PU1

Serial Interface Data Input

DNU

J8

O

O1

Do not use. Reserved

SCIDO

K6

O

O1

Serial Interface Data Output

DNU

E4, F5

-

-

Do not use. Reserved

Misc.

VREG

C5

Power

PWR1

Internal voltage regulator output.

An external ceramic capacitor (4.7

between this pin and system ground.

Power and Ground

VDDQ

C2

Power

PWR1

Power for Host Bus Interface (1.8V/3.0V)

VDDP

C7, H2

Power

PWR1

Power for PSRAM (1.8V)

VDDN

H7

Power

PWR1

Power for NAND Flash (3.0V)

VDD

D4

Power

PWR1

Power for core logic (3.0V)

VSSIO

B3, B6,

J3, J6

Ground

PWR1

GND for IO

VSS

D5, E5,

F4

Ground

PWR1

GND for core logic

T2-1.1 1354(01)

TABLE

2-2: Input/Output (I/O) Buffer Types

I/O Buffer Type

Description

I1

1. Any pin configured as input without internal pull-up or pull-down resistor must not be left unconnected.

I_PU1

Input buffer with internal pull-up

I_PD1

Input buffer with internal pull-down

O1

Output buffer

IO1

I/O buffer

OZ1

Output buffer with tri-state

PWR1

Power or Ground pad

T2-2.0 1354(01)

TABLE

2-1: Pin Descriptions (Continued) (3 of 3)

Symbol

Pin

Location

Pin Type

I/O Type

Name and Functions