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LTC1150 Datasheet(PDF) 10 Page - Linear Technology |
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LTC1150 Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LTC1150 10 1150fb Table 1. Resistor Thermal EMF RESISTOR TYPE THERMAL EMF/°C GRADIENT Tin Oxide ~mV/°C Carbon Composition ~450µV/°C Metal Film ~20µV/°C WireWound Evenohm ~2µV/°C Manganin ~2µV/°C PACKAGE-INDUCED OFFSET VOLTAGE Package-induced thermal EMF effects are another impor- tant source of errors. It arises at the copper/kovar junctions formed when wire or printed circuit traces contact a package lead. Like all the previously mentioned thermal EMF effects, it is outside the LTC1150’s offset nulling loop and cannot be cancelled. Metal can H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC1150 is actually set by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from 0.5 to 3 minutes, depending on package type. ALIASING Like all sampled data systems, the LTC1150 exhibits aliasing behavior at input frequencies near the sampling frequency. The LTC1150 includes a high-frequency correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications. For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC1051/53 data sheet. SYNCHRONIZATION OF MULTIPLE LTC115O’S When synchronization of several LTC1150’s is required, one of the LTC1150’s can be used to provide the “master” clock to control over 100 “slave” LTC1150’s. The master clock, coming from Pin 8 of the master LTC1150, can directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC1150’s will be pulled up to VS. If all the LTC1150’s are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC1150’s. LEVEL SHIFTING THE CLOCK Level shifting is needed if the clock output of the LTC1150 in ±15V operation must interface to regular 5V logic circuits. Figures 2 and 3 show some typical level shifting circuits. When operated from single 5V or ±5V supplies, the LTC1150 clock output at Pin 8 can interface to TTL or CMOS inputs directly. LOW SUPPLY OPERATION The minimum supply for proper operation of the LTC1150 is typically below 4.0V (±2.0V). In single supply applica- tions, PSRR is guaranteed down to 4.7V (±2.35V) to ensure proper operation down to the minimum TTL specified voltage of 4.75V. Figure 2. Output Level Shift (Option 1) Figure 3. Output Level Shift (Option 2) LTC1150 • AI02 10k 10k 15V –15V 5V 2 3 7 8 6 4 LTC1150 + – LOGIC CIRCUIT LTC1150 • AI03 10k 100pF GND 10k 15V –15V 5V 5V 2 3 7 8 6 4 LTC1150 + – LOGIC CIRCUIT APPLICATIO S I FOR ATIO |
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