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MAX2023 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX2023 Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 8 page which is rejected. Note that the sideband suppression is about 45dB typical down from the desired sideband. The desired sideband power level should be approximately +3dBm (+6dBm output power including 3dB pad loss). Phase and amplitude differences at the I and Q inputs result in degradation of the sideband suppression. Note that the spectrum analyzer’s uncalibrated absolute mag- nitude accuracy is typically no better than ±1dB. Detailed Description The MAX2023 is designed for upconverting (downcon- verting) to (from) a 1500MHz to 2300MHz RF from (to) baseband. Applications include multicarrier 1500MHz to 2300MHz GSM/EDGE, cdma2000, and WCDMA. Direct upconversion (downconversion) architectures are advantageous since they significantly reduce transmitter (receiver) cost, part count, and power consumption com- pared to traditional heterodyne conversion systems. The MAX2023 integrates internal baluns, an LO buffer, a phase splitter, two LO driver amplifiers, two matched double-balanced passive mixers, and a wideband quad- rature combiner. The MAX2023’s high-linearity mixers, in conjunction with the part’s precise in-phase and quadra- ture channel matching, enable the device to possess excellent dynamic range, ACLR, 1dB compression point, and LO and sideband suppression characteristics. These features make the MAX2023 ideal for multicarrier genera- tion, like cdma2000 or WCDMA. The MAX2023 EV kit circuit allows for thorough analysis and a simple design-in. Supply-Decoupling Capacitors The MAX2023 has several RF processing stages that use the various VCC pins. While they have on-chip decoupling, off-chip interaction between them can degrade gain, linearity, carrier suppression, and output power. Proper voltage-supply bypassing is essential for high-frequency circuit stability. C1, C6, C7, C10, and C13 are 22pF supply-decoupling capacitors used to filter high-frequency noise. C2, C5, C8, C11, and C12 are larger 0.1µF capacitors used for filtering lower-frequency noise on the supply. DC-Blocking Capacitors The MAX2023 has internal baluns at the RF output and LO input. These inputs have almost 0Ω resistance at DC, so DC-blocking capacitors C3 and C9 are used to prevent any external bias from being shunted directly to ground. LO Bias The bias current for the integrated LO buffer is set with resistor R1 (432Ω ±1%). Resistors R2 (562Ω ±1%) and R3 (301Ω ±1%) set the bias currents for the LO driver amplifiers. Increasing the value of R1, R2, and R3 reduces the current, but the device operates at reduced performance levels. Doubling the values of R1, R2, and R3 reduces the total current by approximately 140mA, but degrades OIP3 by approximately 6dB. IF Bias LO leakage nulling is usually accomplished by adjust- ing the external driving DACs to produce an offset in the common-mode voltage to compensate for any imbalance from I+ to I- and from Q+ to Q-. The EV kit has an added feature to null the LO leakage if the above method is not available. To enable this added feature, first install 8kΩ resistors for R8 through R11 (see Figure 3 for schematic details). To minimize cross coupling of the BB signals, consider adding in the C22 through C25 bypass capacitors. For this method to work, a DC-coupled source impedance (typically 50Ω) needs to appear on all four baseband inputs to form voltage-dividers with the 8kΩ injection resistors. Use a shunt to connect pin 1 of J7 to pin 2 of J7 and a second shunt to connect pin 1 of J8 to pin 2 of J8. Set two DC supplies to 0V and connect one to QBIAS (TP4) and one to IBIAS (TP3). Observe the LO leakage level out of the RF port and slowly adjust the QBIAS positive and observe whether the LO leakage increase or decreases. If the LO leakage decreases, the polarity of the offset is correct. If the LO leakage increases, QBIAS can be adjusted negative or the shunt can be moved on J8 to connect pin 2 to pin 3. Perform the same adjustment and method to the IBIAS (TP3) supply. Optimize the QBIAS and IBIAS voltages to null out the LO leakage. External Diplexer LO leakage at the RF port can be nulled to a level less than -80dBm by introducing DC offsets at the I and Q ports. However, this null at the RF port can be compro- mised by an improperly terminated I/Q IF interface. Care must be taken to match the I/Q ports to the dri- ving DAC circuitry. Without matching, the LO’s sec- ond-order (2fLO) term may leak back into the modula- tor’s I/Q input port where it can mix with the internal LO signal to produce additional LO leakage at the RF out- put. This leakage effectively counteracts against the LO nulling. In addition, the LO signal reflected at the I/Q IF port produces a residual DC term that can disturb the nulling condition. MAX2023 Evaluation Kit _______________________________________________________________________________________ 3 |
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