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LT1175CS8-5 Datasheet(PDF) 5 Page - Linear Technology |
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LT1175CS8-5 Datasheet(HTML) 5 Page - Linear Technology |
5 / 16 page 5 LT1175 1175fd TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT CURRENT (A) 0 20 16 12 8 4 0 0.2 0.4 0.3 0.5 1175 G10 0.1 0.6 0.7 POWER TRANSISTOR IN DROPOUT TJ = –55°C TJ = 25°C VIN – VOUT ≥ 3V TJ = 25°C VIN – VOUT = 2V TJ = 25°C GND pin Current FREQUENCY (Hz) 100 80 60 40 20 0 10 1k 10k 1M 100 100k VOUT = 12V (ADJUSTABLE) IOUT = 100mA VIN – VOUT = 2V COUT = 1µF TANT 1175 G11 RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN 25mA AND 500mA. LARGER OUTPUT CAPACITORS DO NOT IMPROVE REJECTION FOR FREQUENCIES BELOW 50kHz. AT VERY LIGHT LOADS, REJECTION WILL IMPROVE WITH LARGER OUTPUT CAPACITORS VOUT = 12V (ADJUSTABLE) WITH 0.1µF ACROSS DIVIDER RESISTOR VOUT = 5V (FIXED) Ripple Rejection microamperes of current (see Typical Performance Char- acteristics). Maximum voltage on the SHDN pin is 15V, – 20V with respect to the GND pin and 35V, – 5V with respect to the negative input pin. ILIM Pins: The two current limit pins are emitter sections of the power transistor. When left open, they float several hundred millivolts above the negative input voltage. When shorted to the input voltage, they increase current limit by a minimum of 200mA for ILIM2 and 400mA for ILIM4. These pins must be connected only to the input voltage, either directly or through a resistor. OUTPUT Pin: The OUTPUT pin is the collector of the NPN power transistor. It can be forced to the input voltage, to ground or up to 2V positive with respect to ground without damage or latchup (see Output Voltage Reversal in Appli- cations Information section). The LT1175 has foldback current limit, so maximum current at the OUTPUT pin is a function of input-to-output voltage. See Typical Perfor- mance Characteristics. GND Pin: The GND pin has a quiescent current of 45µA at zero load current, increasing by approximately 10µA per mA of output current. At 500mA output current, GND pin current is about 5mA. Current flows into the GND pin. SENSE Pin: The SENSE pin is used in the adjustable version to allow custom selection of output voltage, with an external divider set to generate 3.8V at the SENSE pin. Input bias current is typically 75nA flowing out of the pin. Maximum forced voltage on the SENSE pin is 2V and –10V with respect to GND pin. The fixed 5V version utilizes the SENSE pin to give true Kelvin connections to the load or to drive an external pass transistor for higher output currents. Bias current out of the 5V SENSE pin is approximately 12µA. Separating the SENSE and OUTPUT pins also allows for a new loop compensation technique described in the Applications Information section. SHDN Pin: The SHDN pin is specially configured to allow it to be driven from either positive voltage logic or with negative only logic. Forcing the SHDN pin 2V either above or below the GND pin will turn the regulator on. This makes it simple to connect directly to positive logic signals for active low shutdown. If no positive voltages are available, the SHDN pin can be driven below the GND pin to turn the regulator on. When left open, the SHDN pin will default low to a regulator “on” condition. For all voltages below absolute maximum ratings, the SHDN pin draws only a few PIN FUNCTIONS |
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