Low-Voltage IF Transceiver

with Limiter and RSSI

10

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_______________Detailed Description

The following sections describe each of the blocks

shown in Figure 1.

Receiver

The receiver consists of two basic blocks: the image-

reject downconverter mixer and the limiter/RSSI section.

The receiver inputs are the RXIN, RXIN pins, which

should be AC coupled and may require a matching net-

work, as shown in the

Typical Operating Circuit. To

design a matching network for a particular application,

refer to the

Applications Information section and the

receiver input impedance plots in the

Typical Operating

Characteristics.

Image-Reject Mixer

The downconverter is implemented using an image-

reject mixer consisting of an input buffer with dual out-

puts, each of which is fed to a double-balanced mixer.

The LO signal is generated by an on-chip oscillator and

an external tank circuit. The buffered oscillator signal

drives a quadrature phase generator that provides two

outputs with 90° of phase shift between them. This pair

of LO signals is fed to the two receive mixers. The

mixer’s outputs are then passed through a pair of

phase shifters, which provide 90° of phase shift across

their outputs. The resulting two signals are then

summed together. The final phase relationship is such

that the desired signal is reinforced, and the image sig-

nal is largely canceled. The downconverter mixer’s

0°

RXIN

RXIN

90°

0°

MIXOUT

LIMIN

VREF

CZ

CZ

IF BPF

LIMITER

LIMOUT

RSSI

RXEN

TXEN

LIMOUT

VGA

OFFSET

CORRECTION

RECEIVE IMAGE-REJECT MIXER

TRANSMIT IMAGE-REJECT MIXER AND VGA/PA

Σ

Σ

RSSI

90°

TANK

TANK

OSCOUT

TXOUT

PA

VGA

TXOUT

0°

90°

LO PHASE

SHIFTER

TXIN

TXIN

GC

VOLTAGE GAIN

AND BIAS CONTROL

BIAS

GM

MAX2511

Figure 1. Functional Diagram