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P500-16TCL Datasheet(PDF) 2 Page - PhaseLink Corporation |
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P500-16TCL Datasheet(HTML) 2 Page - PhaseLink Corporation |
2 / 6 page (Preliminary) PLL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/12/06 Page 2 DIE PAD LAYOUT DIE SPECIFICATIONS Name Value Size 39 x 32 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil PACKAGE PIN and DIE PAD ASSIGNMENT Pin# Die Pad Position Name SOP-8 SOT23-6 X ( µm) Y ( µm) Type Description XIN 1 6 94.183 768.599 I Crystal input pin. VCON 2 5 94.157 605.029 P Frequency Control Voltage input pin. DIVSEL 3 - 94.183 331.756 I Divider Selection input pin. Default Logic 1 for SOT23 package. See Divider Selection Logic Levels table on Page 1. GND 4 4 94.193 140.379 P Ground pin. CLK 5 3 715.472 203.866 O Output clock pin. VDD 6 2 715.307 455.726 P VDD power supply pin. OE 7 - 715.472 626.716 I Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Default “Enabled” (Logic 1) for SOT23 package. XOUT 8 1 476.906 888.881 I Crystal output pin. 5 Y X (0,0) (812,986) 32 mil 8 6 2 3 4 7 DIE ID: PLL500-15: C500A A1111-12 PLL500-16: C500A A1111-11 1 XIN DIVSEL^ CLK GND VCON XOUT OE^ VDD Note: ^ denotes internal pull up |
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