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TDA1388 Datasheet(PDF) 6 Page - NXP Semiconductors |
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TDA1388 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 24 page 1996 Jul 17 6 Philips Semiconductors Objective specification Bitstream continuous calibration filter-DAC for CD-ROM audio applications TDA1388 FUNCTIONAL DESCRIPTION The TDA1388 CMOS DAC incorporates an up-sampling digital filter, a sample-and-hold register, a noise shaper, continuously calibrated current sources, line amplifiers and headphone amplifiers. The 1fs input data is increased to an oversampled rate of 64fs. This high-rate oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st-order analog post-filtering. System clock The TDA1388 accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs and 384fs. The system clock must be locked in frequency to the I2S-bus input signals. Table 1 System clock selection Multiple format input interface The TDA1388 supports the following data input formats; • I2S-bus with data word length of up to 20 bits. • LSB justified serial format with data word length of 16, 18 or 20 bits. SYSSEL DESCRIPTION 0 256fs 1 384fs Table 2 Data input formats The input formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. Input mode The TDA1388 has two input modes, a static-pin mode and a microcontroller mode. In the static-pin mode, the digital sound processing features such as mute left, mute right and de-emphasis are controlled by external pins. The other digital sound processing features have a default value. In the microcontroller mode, all the digital sound processing features can be controlled by the microcontroller. The controllable features are: • De-emphasis • Volume left channel • Volume right channel • Flat/min/max switch • Bass boost • Treble • Channel manipulation modes. The selection of one of the two modes is controlled by the ACP pin. When this pin is at logic 0 then the static pin mode will be selected. When the pin is at logic 1 then the microcontroller mode will be selected. IF1 IF2 FORMAT 00 I2S-bus 0 1 LSB-justified, 16 bits 1 0 LSB-justified, 18 bits 1 1 LSB-justified, 20 bits Table 3 Selectable values of the digital sound processing features FEATURES STATIC-PIN MODE MICROCONTROLLER MODE De-emphasis 0 Hz or 44.1 kHz 0 Hz or 44.1 kHz Volume left channel 0 dB (fixed) 0 dB to −∞ dB Volume right channel 0 dB (fixed) 0 dB to −∞ dB Flat/min/max switch flat (fixed) flat/min/max Bass boost flat set (fixed) flat, min or max set Treble flat set (fixed) flat, min or max set Mute left channel external pin selectable (see Table 4) Mute right channel external pin selectable (see Table 4) Channel manipulation modes L_CHANNEL = L (fixed) selectable (see Table 10) R_CHANNEL = R (fixed) |
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