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MH8D64AKQC-10 Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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MH8D64AKQC-10 Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
4 / 40 page MH8D64AKQC-75,-10 536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0419-0.1 17.May.2001 Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI LSIs MITSUBISHI ELECTRIC 4 PIN FUNCTION CK0-2,/CK0-2 Input Clock: CK0-2 and /CK0-2 are diff erential clock inputs. All address and control input signals are sampled on the crossing of the positiv e edge of CK0-2 and negativ e edge of /CK0-2. Output (read) data is ref erenced to the crossings of CK0-2 and /CK0-2 (both directions of c rossing). CKE0 Input Clock Enable: CKE0-1 controls internal clock. When CKE0-1 is low, internal clock f or the f ollowing cyc le is ceased. CKE0-1 is also used to select auto / self ref resh. After self ref resh mode is started, CKE0-1 becomes asy nchronous input. Self ref resh is maintained as long as CKE0-1 is low. /S0 Input Chip Select: When /S0-1 is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-11 Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specif ied by A0-11. The Column Address is specif ied by A0-8. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is perf ormed. When A10 is high at a precharge command, all banks are precharged. BA0-1 Input DQ 0-64 Input / Output DQS0-7 Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. Bank Address: BA0-1 specify one of f our banks in SDRAM to which a command is applied. BA0-1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. SYMBOL TYPE DESCRIPTION Input Vref Input SSTL_2 reference voltage. Vddspd Power Supply Power Supply for SPD SDA Input / Output This is a bidirectional pin used to transf er data into or out of the SPD EEPROM. A resistor must be connected to Vdd to act as a pullup. SCL Input / Output This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected f rom the SCL to Vdd to act as a pullup. SA0-2 Address pins used to select the Serial Presence Detect. Input DM0-7 Input / Output Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM0-7 is sampled HIGH along with that input data during a WRITE access. DM0-7 are sampled on both edges of DQS0-7. Although DM pins are input only, the DM0-7 loading matches the DQ0-63 and DQS0-7 loading. VddID Vdd identif ication f lag Output |
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