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LBMG Datasheet(PDF) 11 Page - Linear Technology |
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LBMG Datasheet(HTML) 11 Page - Linear Technology |
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11 / 16 page  11 LT3014 3014fb OUTPUT VOLTAGE (V) 0 50 45 40 30 35 25 20 15 10 5 0 8 3014 F04 2 135 79 46 10 TJ = 25°C VIN = 0V VOUT = VADJ CURRENT FLOWS INTO OUTPUT PIN ADJ PIN ESD CLAMP APPLICATIO S I FOR ATIO In situations where the ADJ pin is connected to a resistor divider that would pull the ADJ pin above its 7V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, a resistor divider is used to provide a regulated 1.5V output from the 1.22V reference when the output is forced to 60V. The top resistor of the resistor divider must be chosen to limit the current into the ADJ pin to less than 5mA when the ADJ pin is at 7V. The 53V difference between the OUT and ADJ pins divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 10.6k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage, or is left Figure 4. Reverse Output Current open circuit. Current flow back into the output will follow the curve shown in Figure 4. The rise in reverse output current above 7V occurs from the breakdown of the 7V clamp on the ADJ pin. With a resistor divider on the regulator output, this current will be reduced depending on the size of the resistor divider. When the IN pin of the LT3014 is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current will typically drop to less than 2 µA. This can happen if the input of the LT3014 is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN pin will have no effect on the reverse output current when the output is pulled above the input. |
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