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LTC2617IDE Datasheet(PDF) 3 Page - Linear Technology |
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LTC2617IDE Datasheet(HTML) 3 Page - Linear Technology |
3 / 20 page 3 LTC2607/LTC2617/LTC2627 26071727f ELECTRICAL C C HARA TERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSR Power Supply Rejection VCC ±10% –80dB ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA ● 0.032 0.15 Ω VREF = VCC = 2.7V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA ● 0.035 0.15 Ω DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±4 µV Due to Load Current Change ±3 µV/mA Due to Powering Down (per channel) ±30 µV ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC ● 15 36 60 mA Code: Full Scale; Forcing Output to GND ● 15 37 60 mA VCC = 2.7V, VREF = 2.7V Code: Zero Scale; Forcing Output to VCC ● 7.5 22 50 mA Code: Full Scale; Forcing Output to GND ● 7.5 30 50 mA Reference Input Input Voltage Range ● 0VCC V Resistance Normal Mode ● 44 64 80k Ω Capacitance 30 pF IREF Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA Power Supply VCC Positive Supply Voltage For Specified Performance ● 2.7 5.5 V ICC Supply Current VCC = 5V (Note 3) ● 0.66 1.3 mA VCC = 3V (Note 3) ● 0.52 1 mA DAC Powered Down (Note 3) VCC = 5V ● 0.4 1 µA DAC Powered Down (Note 3) VCC = 3V ● 0.10 1 µA Digital I/O (Note 11) VIL Low Level Input Voltage (SDA and SCL) ● 0.3VCC V VIH High Level Input Voltage (SDA and SCL) ● 0.7VCC V VIL(LDAC) Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V ● 0.8 V VCC = 2.7V to 5.5V ● 0.6 V VIH(LDAC) High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V ● 2.4 V VCC = 2.7V to 3.6V ● 2.0 V VIL(CAn) Low Level Input Voltage on CA n See Test Circuit 1 ● 0.15VCC V ( n = 0, 1, 2) VIH(CAn) High Level Input Voltage on CA n (n = 0, 1, 2) See Test Circuit 1 ● 0.85VCC V RINH Resistance from CA n (n = 0, 1, 2) See Test Circuit 2 ● 10 k Ω to VCC to Set CAn = VCC RINL Resistance from CA n (n = 0, 1, 2) See Test Circuit 2 ● 10 k Ω to GND to Set CA n = GND RINF Resistance from CA n (n = 0, 1, 2) See Test Circuit 2 ● 2M Ω to VCC or GND to Set CAn = Float VOL Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), ● 20 + 0.1CB 250 ns CB = 10pF to 400pF (Note 9) tSP Pulse Width of Spikes Suppressed by Input Filter ● 050 ns IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC ● 1 µA CIN I/O Pin Capacitance Note 12 ● 10 pF CB Capacitive Load for Each Bus Line ● 400 pF CCAX External Capacitive Load on Address ● 10 pF Pins CA n (n = 0, 1, 2) |
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