LTC3221/

LTC3221-3.3/LTC3221-5

6

3221f

The LTC3221 family uses a switched capacitor charge pump

comparator (CMP in the Block Diagram) and keeping it

goes above the upper trip point of CMP, or if the upper

Shutdown Mode

The ⎯S⎯H⎯D⎯N pin is a CMOS input with a threshold voltage

of approximately 0.8V. The LTC3221-3.3/ LTC3221-5 are

in shutdown when a logic low is applied to the ⎯S⎯H⎯D⎯N

pin. In shutdown mode, all circuitry is turned off and the

LTC3221-3.3/ LTC3221-5 draw only leakage current from

input, it should never be allowed to float.

When ⎯S⎯H⎯D⎯N is asserted low, the charge pump is first dis-

abled, but the LTC3221-3.3/LTC3221-5 continue to draw

5µA of supply current. This current will drop to zero when

OPERATIO

(Refer to Block Diagrams)

LTC3221-3.3/LTC3221-5

LTC3221

CMP

SHDN

GND

1

5

2

4

6

3

–

+

CONTROL

CMP

FB

GND

1

5

2

4

6

–

+

CONTROL

3

2

1

2

1

2

1

2

1

3221 BD

BLOCK DIAGRA

PI FU CTIO S

C+ (Pin 1): Flying Capacitor Positive Terminal.

C– (Pin 2): Flying Capacitor Negative Terminal.

⎯S⎯H⎯D⎯N (Pin 3) (LTC3221-3.3/LTC3221-5): Active Low

Shutdown Input. A low on ⎯S⎯H⎯D⎯N disables the LTC3221-3.3/

LTC3221-5. ⎯S⎯H⎯D⎯N must not be allowed to float.

FB (Pin 3) (LTC3221): Feedback. The voltage on this pin

is compared to the internal reference voltage (1.23V) by

the error comparator to keep the output in regulation. An

to program the output voltage.

GND (Pin 4): Ground. Should be tied to a ground plane

for best performance.

with a 2.2µF low ESR capacitor.

low ESR capacitor as close as possible to the pin.

Exposed Pad (Pin 7) Ground. The exposed pad must be

soldered to PCB ground to provide electrical contact and

optimum thermal performance.