AMIS-710650-A6: Color CIS Module

Data Sheet

Analog Video Output

CLK

1 Pixel

50%

VOUT

90%

50%

Prt

TS

Figure 5: Pixel Timing

ll tests were conducted at the typical pixel rate of 3.0MHz.

ck Timing Characteristics for Timing Diagrams

A

Table 6: Clo

Parameter

Symbol

Min.

Typ.

Max.

Units

Clock cycle time

CLKp

250

250

ns

Clock pulse width

CLKpw

125

ns

Clock duty cycle

50

%

Prohibit crossing time SP

tprh

30

ns

Data setup time

Tset

30

ns

Data hold time

Thold

30

ns

Signal delay time

tdl

50

ns

Signal settling time

tst

130

ns

Signal fall time

tsigf

60

ns

Note

patible with CMOS clock drivers.

clock cycle time, as with minimum FREQ, must be consistent with maximum TINT. See Table 3, Note 3.

s:

(1)

All of the symbol definitions used in Table 6 are shown in the figures in Section 9.0. The clocks, CP and SP are com

(2)

Maximum

10.0 Maximum Ratings

Table 7: Maximum Ratings (Not to be Used for Contin

ation)

uous Oper

Parameter

S

l

ymbo

Spe

n

cificatio

Note

Power supply voltage

VDD

3.3V

Input voltage

VIN

VDD

SP & CP

Ambient temperature

TA (PCB surface)

-

Operational storage

0 to 50

10 to +75

Ambient humidity

HA

0 to 80%

Non-condensing

Maximum operating case temperature

PCB temperature

70 C

°

6

AMI Semiconductor – Aug. 06, M-20611-001

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