4

AMI Semiconductor - Rev. 3.0

www.amis.com

When not using the REF input, it is preferred to leave it floating

This device is a read/write slave device meeting all

call." The bus has to be controlled by a master

device that generates the serial clock SCL,

controls bus access and generates the START

and STOP conditions while the device works as a slave. Both

master and slave can operate as a transmitter or receiver, but

the master device determines which mode is activated. A

device that sends data onto the bus is defined as the

transmitter, and a device receiving data as the receiver.

The FS7145 supports nearly instantaneous adjustment of the

output CLK phase by the SYNC input. Either edge direction of

SYNC (positive-going or negative-going) is supported.

Example (positive-going SYNC selected): Upon the negative

edge of SYNC input, a sequence begins to stop the CLK

output.

Upon the positive edge, CLK resumes operation,

synchronized to the phase of the SYNC input (plus a

deterministic delay). This is performed by control of the device

post-divider. Phase resolution equal to ½ of the VCO period

can be achieved (approximately down to 2ns).

4.1.6 Feedback Divider Source MUX

The source of frequency for the feedback divider may be

selected to be either the output of the post divider or the output

of the VCO by the FBKDSRC bit.

Ordinarily, for frequency synthesis, the output of the VCO is

used.

Use the output of the post divider only where a

deterministic phase relationship between the output clock and

reference clock are desired (line-locked mode, for example).

4.1.7 Device Shutdown

Two bits are provided to effect shutdown of the device if

desired, when it is not active. SHUT1 disables most externally

observable device functions.

SHUT2 reduces device

quiescent current to absolute minimum values. Normally, both

bits should be set or cleared together.

Serial communications capability is not disabled by either

SHUT1 or SHUT2.

4.2 Differential Output Stage

The differential output stage supports both CMOS and pseudo-

ECL (PECL) signals. The desired output interface is chosen via

the programming registers.

If a PECL interface is used, the transmission line is usually

terminated using a Thévenin termination. The output stage can

only sink current in the PECL mode, and the amount of sink

current is set by a programming resistor on the LOCK/IPRG

pin. The ratio of output sink current to IPRG current is 13:1.

Source current for the CLKx pins is provided by the pull-up

resistors that are part of the Thévenin termination.

4.2.1 Example

Assume that it is desired to connect a PECL-type fanout buffer

right next to the FS7140.

Further assume:

Then:

R1 (from CLKP and CLKN output to VDD) =

75 * 3.3 / 2.4 =

103 ohms

R2 (from CLKP and CLKN output to GND) =

75 * 3.3 / (3.3 - 2.4) =

275 ohms

Rprgm (from VDD to IPRG pin) =

26 * (3.3 * 75) / (2.4 - 1.6) / 3 =

2.68 Kohms

4.3 SYNC Circuitry