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PI0128WSN Datasheet(PDF) 5 Page - AMI SEMICONDUCTOR |
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PI0128WSN Datasheet(HTML) 5 Page - AMI SEMICONDUCTOR |
5 / 8 page PI0128WSN, PI0256WSN, PI0512WSN Engineering Data Sheet Page 5 of 8 Revised March 21, 2002 Clock and Voltage Requirements The clocking requirements are relatively simple. As it was indicated in Figure 5 and Table 1, there are only two input signals that require clocked inputs. They are CLK, the clock for the shift register, and START, the shift register start pulse. The timing specifications and the symbol definition for Figure 6 are listed in Table 2. The control clock amplitudes for I/Os are compatible with the 5-Volt CMOS devices. Figure 6. Timing diagram. Table 2. Symbol definitions and timing specifications for timing diagram. Item Symbol Min Typical Max Units Clock cycle time to 666 (128WSN) 666 (256WSN) 1000 (512WSN) 10000 ns Clock high pulse width twh 566 (128WSN) 566 (256WSN) 900 (512WSN) ns Clock low pulse width twl 100 ns Clock duty cycle 1 50 99 % Data setup time tds 100 ns Data hold time tdh 100 ns EOS low-to-high delay telh 400 ns EOS high-to-low delay tehl 400 ns Signal delay time tsd 50 ns Signal settling time tsh 566 (128WSN) 566 (256WSN) 900 (512WSN) ns Signal settle to clock edge tsch 0 ns |
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