CY28352

Rev 1.0, November 21, 2006

Page 2 of 7

Zero Delay Buffer

When used as a zero delay buffer the CY28352 will likely be

in a nested clock tree application. For these applications the

CY28352 offers a clock input as a PLL reference. The

CY28352 can then lock onto the reference and translate with

near zero delay to low-skew outputs. For normal operation, the

external feedback input, FBIN, is connected to the feedback

output, FBOUT. By connecting the feedback output to the

feedback input the propagation delay through the device is

eliminated. The PLL works to align the output edge with the

input reference edge thus producing a near zero delay. The

reference frequency affects the static phase offset of the PLL

and thus the relative delay between the inputs and outputs.

bypassed for test purposes.

Power Management

The individual output enable/disable control of the CY28352

allows the user to implement unique power management

schemes into the design. Outputs are three-stated when

disabled through the two-line interface as individual bits are

set low in Byte0 and Byte1 registers. The feedback output

FBOUT cannot be disabled via two line serial bus. The

enabling and disabling of individual outputs is done in such a

manner as to eliminate the possibility of partial “runt” clocks.

Pin Number

Pin Name

I/O

Pin Description

Electrical

Characteristics

8CLKIN

I

Complementary Clock Input.

Input

20

FBIN

I

Feedback Clock Input. Connect to FBOUT for accessing the

PLL.

Input

2,4,13,17,24,

26

CLKT(0:5)

O

Clock Outputs

Differential Outputs

1,5,14,16,25,

27

CLKC(0:5)

O

Clock Outputs

19

FBOUT

O

Feedback Clock Output. Connect to FBIN for normal operation.

A bypass delay capacitor at this output will control Input

Reference/Output Clocks phase relationships.

Output

7SCLK

I

Serial Clock Input. Clocks data at SDATA into the internal

register.

Data Input for the two line

serial bus

22

SDATA

I/O

Serial Data Input. Input data is clocked to the internal register to

enable/disable individual outputs. This provides flexibility in

power management.

Data Input and Output for

the two line serial bus

3,12,23

VDD

2.5V Power Supply for Logic

2.5V Nominal

10

AVDD

2.5V Power Supply for PLL

2.5V Nominal

6,15,28

GND

Ground

11

AGND

Analog Ground for PLL

9, 18, 21

NC

Not Connected

Function Table

Inputs

Outputs

PLL

VDDA

CLKIN

FBOUT

GND

L

L

H

L

BYPASSED/OFF

GND

H

H

L

H

BYPASSED/OFF

2.5V

L

L

H

L

On

2.5V

H

H

L

H

On

2.5V

<20 MHz

Hi-Z

Hi-Z

Hi-Z

Off

Notes:

1. A bypass capacitor (0.1

μF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their

high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.

2. Each output pair can be three-stated via the two-line serial interface.