SN75LVDS31, SN75LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359C – JUNE 1999 – REVISED JUNE 2001

8

POST OFFICE BOX 655303

APPLICATIONS INFORMATION

1A

1Y

1Z

G

2Z

2Y

2A

GND

VCC

4A

4Y

4Z

G

3Z

3Y

3A

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ZO = 100 Ω

ZO = 100 Ω

ZO = 100 Ω

ZO = 100 Ω

3.3 V

0.1

µF

(see Note A)

0.001

µF

(see Note A)

VCC

See Note B

NOTES: A. Place a 0.1

µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground

plane. The capacitors should be located as close as possible to the device terminals.

B. Unused enable inputs should be tied to VCC or GND as appropriate.

Figure 5. Typical Application Circuit Schematic