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MH8S64DBKG-7 Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor |
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MH8S64DBKG-7 Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor |
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6 / 55 page  MH8S64DBKG -7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM MITSUBISHI LSIs ( / 55 ) MITSUBISHI ELECTRIC 17.Sep.1999 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0340-0.0 PIN FUNCTION Input Master Clock:All other inputs are referenced to the ris ing edge of CK CKE0, CKE1 Input Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. /S0, /S1 Input Chip Select: When /S is high,any command means No Operation. /RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands. A0-11 Input A0-11 specify the Row/Column Address in conjunction with BA0,1.The Row Address is specified by A0-11.The Column Address is specified by A0-7.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. BA0,1 Input Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands DQ0-63 Input/Output Data In and Data out are referenced to the rising edge of CK DQMB0-7 Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle. Vdd,Vss Power Supply Power Supply for the memory mounted module. SCL SDA Input Output Serial clock for serial PD Serial data for serial PD 6 CLK (CLK0 ~ CLK1) |
Similar Part No. - MH8S64DBKG-7 |
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Similar Description - MH8S64DBKG-7 |
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