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MH8S64DBKG-7L Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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MH8S64DBKG-7L Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
4 / 55 page MH8S64DBKG -7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM MITSUBISHI LSIs ( / 55 ) MITSUBISHI ELECTRIC 17.Sep.1999 Preliminary Spec. Some contents are subject to change without notice. MIT-DS-0340-0.0 4 Serial Presence De tect Table I Byte Function described SPD enrty data SPD DATA(hex) 0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly A0-A7 08 5 # Module Banks on this assembly 2BANK 02 6 Data Width of this assembly... x64 40 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). A0 Cycle time for CL=3 10 SDRAM Access from Clock 6ns 60 tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) Non-PARITY 00 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x16 10 14 Error Checking SDRAM data width N/A 00 15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 16 Burst Lengths Supported 1/2/4/8/Full page 8F 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency 2/3 06 19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes non-buffered,non-registered 00 22 SDRAM Device Attributes:General Precharge All,Auto precharge 0E 23 SDRAM Cycle time(2nd highest CAS latency) 13ns D0 Cycle time for CL=2 24 SDRAM Access form Clock(2nd highest CAS latency) 7ns 70 tAC for CL=2 25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 N/A 00 26 SDRAM Access form Clock(3rd highest CAS latency) 27 Precharge to Active Minimum 20ns 14 28 Row Active to Row Active Min. 20ns 14 10ns -8,8L -8,8L -7,7L 10ns A0 6ns 60 -7,7L 29 RAS to CAS Delay Min 20ns 14 30 Active to Precharge Min 50ns 32 |
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