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TMS320TCI6482 Datasheet(PDF) 4 Page - Texas Instruments |
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TMS320TCI6482 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 255 page  www.ti.com 1.3 Functional Block Diagram MDIO EMAC 10/100/1000 Serial Rapid I/O DDR2 Mem Ctlr Device Configuration Logic 64 L1P SRAM/Cache Direct-Mapped 32K Bytes L1D SRAM/Cache 2-Way Set-Associative 32K Bytes Total TCI6482 PLL1 and PLL1 Controller EMIFA HI Boot Configuration I/O Devices UTOPIA(B) VCP2 I2C GPIO16(B) 16 McBSP0(A) RSA RSA RMGII(D) L2 Cache Memory 2096K Bytes L2 ROM 32K Bytes(E) TCP2 McBSP1(A) HPI (32/16)(B) A. McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins. For more detailed information, see the Device Configuration section of this document. C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purpose timers or two 32-bit general-purpose timers or a watchdog timer. D. The PLL2 controller also generates clocks for the EMAC. E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz. DDR2 SDRAM 32 LO Timer1(C) HI LO Timer0(C) PCI66(B) VLYNQ PLL2 and PLL2 Controller(D) GMII RMII MII EDMA 3.0 C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 .L1 .S1 .M1 xx xx .D1 .D2 .M2 xx xx .S2 .L2 M e g a m o d u l e L1P Memory Controller (Memory Protect/Bandwidth Mgmt) Instruction Decode 16-/32-bit Instruction Dispatch Control Registers In-Circuit Emulation SPLOOP Buffer L1D Memory Controller (Memory Protect/Bandwidth Mgmt) Secondary Switched Central Resource TMS320TCI6482 Communications Infrastructure Digital Signal Processor SPRS246F – APRIL 2005 – REVISED MAY 2007 Figure 1-2 shows the functional block diagram of the TCI6482 device. Figure 1-2. Functional Block Diagram Features 4 Submit Documentation Feedback |
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